BU9414FV Datasheet, PDF (9/61 Pages) Rohm – 32bit Audio DSP

BU9414FV
1-3. Control signal specification
○ Bus line, I/O stage electrical specification and timing.
Technical Note
SDAI
t_BUF
t_F
t_LOW
t_R
SCLI
t_HD;STA
t_HD;DAT
P
S
t_HIGH
t_SU;DAT
t_SU;STA
Sr
Fig.1-1: Timing chart
t_HD;STA
t_SU;STO
P
Table 1-1: SDAI and SCLI bus-line characteristic (Unless specified, Ta=25°C, Vcc=3.3V)
Parameter
Code
High-speed mode
Unit
Min.
Max.
1 SCLI clock frequency
fSCL
0
400
kHz
Bus-free-time between "Stop" condition and "Start"
2
t_BUF
1.3
－
μS
condition
3 ^{"Start" condition of hold-time (resending). After this period, t}HD;STA
0.6
the first clock-pulse is generated.
4 LOW status hold-time of SCLI clock
t_LOW
1.3
5 HIGH status hold-time of SCLI clock
t_HIGH
0.6
6 Setup time of resending “Start” condition
t_SU;STA
0.6
7 Data-hold-time
t_HD;DAT
0¹⁾
－
μS
－
μS
－
μS
－
μS
－
μS
8 Data-setup time
9 Rising time of SDAI and SCL signal
10 Fall time of SDAI and SCL signal
11 Setup time of "Stop" condition
t_SU;DAT ^500/250/15
－
ns
0
t_R
20+Cb
300
ns
t_F
20+Cb
300
ns
t_SU;STO
0.6
－
μS
12 Capacitive load of each bus-line
Cb
－
400
pF
The above-mentioned numerical values are all the values corresponding to V_{IH min} and V_{IL max} level.
1) To exceed an undefined area on falling edged of SCLI, transmission device should internally offer the hold-time of
300ns or more for SDAI signal(V_{IH min} of SCLI signal).
2) Data-setup time changes with setup of MCLK. In MCLK=512fs, data setup time is 150ns.
In MCLK=256fs, data setup time is 250ns. In MCLK=128fs, data setup time is 500ns.
The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.
When problem occurs by any chance, we talk in good faith and correspond.
Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V.
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2012.03 - Rev.A