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BU9414FV Datasheet, PDF (48/61 Pages) Rohm – 32bit Audio DSP | |||
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BU9414FV
Technical Note
8. Command sent after releasing reset
Please send the following command after releasing reset including power supply on.
0. Power supply turning on
â
â Please input the clock from the outside. When the clock is not input, reset can't normally be done.
â
1. Reset release (RESETB="H")
â
2. &hA0[7:0] = C2h ï¼Set PLLA.
â
3. &hF3[5:0] = 08h ï¼Set the dividing frequency ratio of MCLK. Please do as follows to set a value by fs of
MCLK.
ï¼MCLK:512fs=08hã256fs=04hã128fs=02hï¼
â
4. &hF5[3:0] = 01hï¼Set the dividing frequency ratio of PLL.
â
5. &hF6[7:0] = 00hï¼Set the phase adjust command of PLL.
â
6. &hF1[4] = 0ï¼Enable analog input.
â
7. &h08[5:4] = 1h ï¼Select system clock is PLL.
â
8. &hA7[7:0] = F4hï¼Synchronous detection condition setting 1 for PLLA is initialized.
â
9. &hA8[7:0] = 33hï¼Synchronous detection condition setting 2 for PLLA is initialized.
â
10. &hA9[3:0] = 3hï¼Synchronous detection condition setting 3 for PLLA is initialized.
â
11. &hA9[5:4] = 2h or 1h or 0h ï¼Set MCLK.
(Set in â2hâWhile MCLK is 512fs, set in â1hâWhile MCLK is 256fs, set in â0hâWhile MCLK is 128fs.)
â
â It is about 10ms wait until PLL is steady.
â
12. &hAA[7:0] = 80h ï¼A data taking-in position is adjusted.
â
13. Read back &hAA[7] address data and check read result is 0.
â
â It is about 5ms wait until RAM all address clear.
â
14.&h01 = 00h : Set ram clear off.
â
15. Other register setting
&h26[7:0] = **h ï¼Release the mute of the Main output volumeï¼30h=0dBï¼.
&h2C[7:0] = **h ï¼Release the mute of the Sub output volumeï¼30h=0dBï¼.
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2012.03 - Rev.A
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