BU9414FV Datasheet, PDF (10/61 Pages) Rohm – 32bit Audio DSP

BU9414FV
2.Switching of data and clock
I/O system chart of BU9414FV audio data is shown below.
Technical Note
Di_Dg_ii_gta_itl_alin_inp_pu_utt₁1
Dig_Di_it_ga_itl_ai_ln_inp_pu_ut_t2₂
SEL1
SDATA1
SDATA2
DSP CLK
(512fs)
S-P
conversi
on1
S-P
conversi
on2
DSP operation part
This part is performanced by hardware.
Main _Bass
Treble
Func.
Main
P-EQ
Main
EVR
Sub
Sub
SEL2
P-S _{SDATAO1(Main)}
Convers
ion1
P-S _SDATAO2(Sub)
Convers
ion2
P-S
Convers
ion3
SPDIFO
Audio DSP
(BU9414FV)
SEL3
plla_
div
PLLA
mclk_
div
Control I/F
・・・
D Class amp output
(Main SP)
D Class amp output
(Sub Woofer)
Optical output
BU9414FV has 2 digital stereo input and 3 digital stereo output with the same sampling rate.
Output from DSP operation part is converted into I²S mode digital output or S/PDIF mode digital serial output.
System clock uses master clock input from MCLK terminal, makes 512fs multiplying clock in PLL block. Moreover, 256fs
synchronous clock can be output from terminal SYSCLKO, and the clock is supplied to external DAC or D class SP amplifier.
SPDIFO and output data selection of SDATAO1 and SDATAO2 should unify the DSP processing after (post) or processing
before (pre) with all outputs.
2-1. S-P conversion1 input data selection(SEL1)
Default = 0
Select Address
&h03 [ 0 ]
Value
0
1
Operating Description
Input data from SDATA1
Input data from SDATA2
2-2. S-P conversion2 input data selection(SEL1)
Default = 0
Select Address
&h03 [ 4 ]
Value
0
1
Operating Description
Input data from SDATA1
Input data from SDATA2
2-3. Output data selection(SEL2) to P-S conversion1 (SDATAO1 Terminal)
Default = 0
Select Address
&h04 [ 1：0 ]
Value
0
1
2
3
Operating Description
Main data output after DSP is processed.
Sub data output after DSP is processed.
Main data output before DSP is processed.
Sub data output before DSP is processed.
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10/57
2012.03 - Rev.A