BU9414FV Datasheet, PDF (12/61 Pages) Rohm – 32bit Audio DSP

BU9414FV
Technical Note
3. S-P Conversion 1, S-P Conversion 2
BU9414FV has two serial-parallel conversion circuits. （S-P conversion 1, S-P conversion 2）
S-P conversion 1 & 2 receives the audio data of three-wire serial input from terminal and converts it into parallel data.
They select the inputs from LRCKI (2pin), BCKI (40pin), SDATA1 (3pin), and SDATA2(4pin).
Input format has IIS method, left-justified method and right-justified method. Moreover, for bit clock frequency, 64fs or 48fs
can be selected, and when 48fs is selected, the input format becomes the fixed right-justification. In addition, 16bit, 20bit and
24bit inputs can be selected respectively.
Timing chart of each transmission method is shown in the diagram below.
IIS method
IIS方式
LRCKI
BCKI
DATAI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
Left-justified method
左詰方式
LRCKI
BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
DATAI S
S
16bit
20bit
24bit
16bit
20bit
24bit
Right-justified
m^右e^詰th^方od^式
LRCKI
BCKI
DATAI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
48fs
LRCKO
BCKO
DATAO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
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2012.03 - Rev.A