BU9414FV Datasheet, PDF (50/61 Pages) Rohm – 32bit Audio DSP

BU9414FV
Technical Note
10. About a setup of a clock, and the input of a command
The input of MCLK is decided by combination of three kinds of sampling rates (fs=32kHz, 44.1kHz, 48kHz), and three kinds
of magnifications (128 times, 256 times, 512 times).
Sampling rate(fs)
MCLK clock
32kHz
44.1kHz
48kHz
128fs
4.096MHz
5.6448MHz
6.144MHz
256fs
8.192MHz
11.2896MHz
12.288MHz
512fs
16.384MHz
22.5792MHz
24.576MHz
In order that PLL may multiple the dividing output of MCLK, the dividing ratio of MCLK is not concerned with a sampling rate
like explanation in Chapter 8, but is decided by the magnification of MCLK.
MCLK clock
&hF3[5:0]
128fs
04h
256fs
08h
512fs
10h
Therefore, as for the case of the input of 4.096MHz-6.144NHz, and a 256fs setup, in the input frequency of MCLK, in a 128fs
setup, a 16.384MHz - 24.576MHz input serves as a range which can be operated in a 8.192MHz - 12.288MHz input and a
512fs setup.
MCLK
&hF3[5:0]
DIV
I2C
CONTROL LOGIC
PLLA
PLL_DIV
S
E
L
1
DSP
AUDIO IF
BU9414FV
Clock line
ERROR_DET
&h08[5:4]
S
E
SYSCLKO
L
2
The clock system figure of BU9414FV is as mentioned above.
(1) In the case of &h08 [5:4] =1, the block of an above figure light blue operates with a PLL clock.
(2) In the case of &h08 [5:4] =0, the block of an above figure light blue operates by MCLK.
Be careful of the following points at the time of a command input.
In (1), a part of blocks containing DSP are operating with the clock of PLL.
Therefore, even if MCLK is the range which is 4.096MHz - 24.576MHz, when a setup of PLL and the setup of &hF3 are not
performed correctly, a command may not be received other than command &h08 of a system control system, &hA0-&hA9,
&hB0-&hBA, &hD0, &hF0 - &hFA.
In (2), the whole operates with the clock of MCLK.
If MCLK is the range which is 4.096MHz - 24.576MHz, all blocks will receive an I2C command.
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2012.03 - Rev.A