BU9414FV Datasheet, PDF (51/61 Pages) Rohm – 32bit Audio DSP

BU9414FV
Technical Note
11. About the change of a sampling rate
11-1.
When a sampling rate change can predict beforehand
When the change of a sampling rate can predict beforehand, please switch a sampling rate in the following
procedures.
1．The mute of the DAC is carried out (MUTEX_SP and MUTEX_DAC are set to L and it is a mute about BD5446.).
↓
2. EVR is set as -infinity.
↓
3. Set prescaler as -infinity.
↓
4. A RAM clearance is carried out by setting it as &h01= C0h.
↓
5. &h08[5:4] = by setting it as 0, the whole clock is switched to MCLK.
↓
6. Switch a sampling rate.
↓
7. Switch to a PLL clock after stabilizing the input of MCLK by setting it as more 10 msec WAIT and &h08 [5:4] =1h,
since it is PLL stability.
↓
8. &hAA[7:0] = 80h ：A data taking-in position is adjusted.
↓
9. Read back &hAA[7] address data and check read result is 0.
↓
○ It is about 5ms wait until RAM all address clear.
↓
10.&h01 = 00h : Set ram clear off.
↓↓
11. Since the coefficient is cleared, please set up DSP.
↓
12. Please cancel a DAC mute.
11-2.
When a sampling rate change cannot predict beforehand
Please do the following work, when the change of a sampling rate cannot predict beforehand, and having switched is
detected.
1．The mute of the DAC is carried out (MUTEX_SP and MUTEX_DAC are set to L and it is a mute about BD5446.).
↓
○When the input of MCLK has stopped, please do not input a command until MCLK is inputted again.
Please perform the following setup, after MCLK is inputted on the frequency of specification within the limits.
↓
2． It is set as &h08[5:4] = 0 and the whole clock is switched to MCLK.
↓
3．Switch to a PLL clock after stabilizing the input of MCLK by setting it as more 10 msec WAIT and &h08 [5:4] =1h,
since it is PLL stability.
↓
4．A RAM clearance is carried out by setting it as &h01= C0h.
↓
5．EVR is set as -infinity.
↓
6．Prescaler is set as -infinity.
↓
7. &hAA[7:0] = 80h ：A data taking-in position is adjusted.
↓
8. Read back &hAA[7] address data and check read result is 0.
↓
○ It is about 5ms wait until RAM all address clear.
↓
9.&h01 = 00h : Set ram clear off.
↓
10．Since the coefficient is cleared, please set up DSP.
↓
11．Please cancel a DAC mute.
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2012.03 - Rev.A