BD9406KS2 Datasheet, PDF (9/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
1-3. Control Signal Specifications
○ Electrical Characteristics and Timing for Bus Line and I/O Stage
Technical Note
SDA
t_BUF
t_F
t_LOW
t_R
SCL
t_HD;STA
t_HD;DAT
P
S
t_HIGH
t_SU;DAT
t_SU;STA
Sr
Fig.1-1: Timing Chart
t_HD;STA
t_SU;STO
P
Chart 1-1: SDA and SCL Bus Line Characteristics (Unless specified, Ta=25℃ and V_DD=3.3V)
Parameters
High-Speed Mode
Symbol
Unit
Min.
Max.
1 SCL clock frequency
fSCL
0
400
kHz
Bus free time between “stop” condition and
2
“start” condition
t_BUF
1.3
－
μS
Hold time (re-transmit) “start” condition.
3
After this period, the first clock pulse is generated.
4 SCL clock LOW state hold time
5 SCL clock HIGH state hold time
6 Re-transmit set-up time of “start” condition
7 Data hold time
8 Data setup time
9 SDA and SCL signal stand-up time
10 SDA and SCL signal stand-down time
11 Set-up time for “stop” condition
t_HD;STA
0.6
－
μS
t_LOW
1.3
－
μS
t_HIGH
0.6
－
μS
t_SU;STA
0.6
－
μS
t_HD;DAT
0¹⁾
－
μS
t_SU;DAT
100
－
ns
t_R
20+Cb
300
ns
t_F
20+Cb
300
ns
t_SU;STO
0.6
－
μS
12 Each bus line’s capacitive load
Cb
－
400
pF
The values above correspond with V_{IH min} and V_{IL max} levels.
1) Because the transmission device exceeds the undefined domain of the SCL fall edge, it is necessary to internally
provide a minimum 300ns
hold time for the SDA signal (of V_{IH min} of SCL signal).
The characteristics above are logical values for design; guarantees in the form of delivery inspections are not offered.
In the event of a problem, comprehensive consultation and support will be provided.
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2012.03 - Rev.A