BD9406KS2 Datasheet, PDF (13/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
Technical Note
2-13. Input Selection to P-S Conversion 1 (SEL10)
Default = 0
Select Address
&h09 [ 7 ]
Value
0
1
Operation Description
Outputs data from AD conversion
Outputs data after conversion to fs=48kHz at ASRC
2-15. Output Selection When Configuring AMCLK4S Pin to S/PDIF Output (SEL2, SEL6, SEL11)
Default = 0
Select Address
&h09 [ 2：0 ]
Value
0
1
2
3
4
5
Operation Description
Inputs data before DSP processing
Outputs data after DSP processing
Outputs data from I2S_IN1 (Only output data in S/PDIF format)
Outputs data from I2S_IN2 (Only output data in S/PDIF format)
Outputs data from I2S_IN3 (Only output data in S/PDIF format)
Outputs data from I2S_IN4 (Only output data in S/PDIF format)
2-16. AMCLK4S Pin In/Output Switching (SEL2)
Default = 0
Select Address
&h09 [ 3 ]
Value
0
1
Operation Description
Clock input
S/PDIF data output (refer to &h11, &h12 and &h13)
There are three types of system clocks used by the DSP or DF+DAC sections of BU9406KS2.
One is the 24.576MHz (512fs) system clock from the XI pin, and the other two are 512fs clocks generated by PLL1
andPLL2 from the input clocks BCKI1~3.
2-17. System Clock Selection of ASRC Input Section (used for up-sampling) (Dotted line ①)
Default = 0
Select Address
&h0A [ 7：6 ]
Value
0
1
2
Operation Description
24.576MHz (512fs) system clock from XI pin
512fs clock extracted from S-P conversion 1 PLL1
512fs clock extracted from S-P conversion 2 PLL2
2-18. System Clock Selection for ASRC Output Section (used for down-sampling), P-S Conversion 2 and S/PDIF Output
(Dotted line ③)
Default = 0
Select Address
&h0A [ 1：0 ]
Value
0
1
2
Operation Description
24.576MHz (512fs) system clock from XI pin
512fs clock extracted from S-P conversion 1 PLL1
512fs clock extracted from S-P conversion 2 PLL2
2-19. System Clock Selection for P-S Conversion 1 (Dotted line ②)
Default = 0
Select Address
&h0A [ 5：4 ]
Value
0
1
2
Operation Description
24.576MHz (512fs) system clock from XI pin
512fs clock extracted from S-P conversion 1 PLL1
512fs clock extracted from S-P conversion 2 PLL2
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2012.03 - Rev.A