BD9406KS2 Datasheet, PDF (10/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
Technical Note
2. Data and Clock Switching
Below is the in/output system diagram for BU9406KS2.
Audio DSP
(BU9406KS2)
AINL,AINR ^{Analog IN}
ADC
DATAI1,BCKI1,LRCKI1
DATAI2,BCKI2,LRCKI2
DATAI3,BCKI3,LRCKI3
DATAI4,BCKI4,LRCKI4
I2S IN1
I2S IN2
I2S IN3
I2S IN4
PLL1
I2S
S-P
Conve
rsion1
S
E
I2S
S-P
Conve
L
rsion2
6 ^PLL2
AMCLKI1
AMCLKI2
AMCLKI3
AMCLKI4S
AMCLK IN1
AMCLK IN2
AMCLK IN3
AMCLK IN4
S _3-State
E
L
7
S
E
L
1
SEL8
③
①
ASRC
DSP Computing Section
This section is actualized by hardware.
AGC
Func. Parame
Main tric EQ
EVR
SEL10
②
P-S
Conve
rsion1
SEL9
CG
Control I/F
P-S
S
Conve
rsion2
E
L
SPDIF
2
Conver
sion
I2S
OUT C
DATAOC,BCKOC,LRCKOC
S
E
S/PDIF
L
11
AMCLKI4S
④
S
E
L
3
DF1
ΔΣ SP OUT
DAC1
AOUTL3,AOUTR3
S
E
L
4
⑤
DF2
ΔΣ LINE OUT
DAC2
AOUTL2,AOUTR2
S
E
L
5
DF3
⑥
16bit
DAC
REC OUT
AOUTL1,AOUTR1
・・・
BU9406KS2 has a 4-line digital stereo input, 1-line analog stereo input, 4-line digital stereo output and 3-line analog stereo
output.
The digital data input to the DSP computing section is first changed to fs=48kHz data at the ASRC (asynchronous sampling
rate converter).
DSP computing section output is changed to either I²S format digital output, S/PDIF format digital serial output or analog
output.
2-1. ASRC Input Selection (SEL1）
Default = 0
Select Address
Value
Operation Description
&h03 [ 5：4 ]
0
Inputs analog signals converted to digital data
1
Inputs via S-P conversion 1 (refer to &h05[5:4])
2
Inputs via S-P conversion 2 (refer to &h05[1:0])
S-P conversions 1 and 2 convert I²C format serial data to 24bit parallel data.
2-2. DF1 Input Selection (SEL1, SEL2, SEL3)
Default = 0
Select Address
&h03 [ 2：0 ]
Value
0
1
2
3
4
Operation Description
Inputs analog signals converted to digital data
Inputs via S-P conversion 1 (refer to &h05[5:4])
Inputs via S-P conversion 2 (refer to &h05[1:0])
Inputs data before DSP processing
Inputs data after DSP processing
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10/34
2012.03 - Rev.A