BD9406KS2 Datasheet, PDF (7/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
Technical Note
1. Command Interface
BU9406KS2 uses the I²C bus format for the command interface with the host CPU.
With BU9406KS2, in addition to write mode, read mode read-out is possible with many registers.
BU9406KS2 assigns a 1-byte select address in addition to the slave address and performs write-in and read-out.
The I²C bus slave mode format is as follows:
MSB
LSB MSB
LSB MSB
S Slave Address
A Select Address
A Data
LSB
AP
S: Start Condition
Slave Address:
Adds either a read mode (H”) or write mode (L”) bit to the slave address (7bit) configured by
I2CADR1 and I2CADR2, sending a total of 8 bits of data. (MSB first)
A: Acknowledge An acknowledge bit is added on to each bit of data transmitted.
When data transmission is being done correctly, “L” is transmitted.
“H” transmission means there was no acknowledge.
Select Address:
BU9406KS2 uses a 1-byte select address. (MSB first)
Data:
Data byte, transmitted data (MSB first)
P:
Stop condition
SDA
MSB 6
5
SCL
Start Condition
When SDA↓, SCL=”H”
LSB
Stop Condition
When SDA↑, SCL=”H”
1-1. Data Write-In
S Slave Address
MSB
A6 A5 A4
1
0
0
A Select Address
A Data
AP
: Master to Slave
: Slave to Master
Slave Address Configuration for BU9406KS2
LSB
Pin Configuration
Write Mode
A3 A2 A1 A0 R/W
I2CADR2 I2CADR1
Slave Address
0
0
0
0
0
0
0
80h
0
1
82h
1
0
84h
1
1
86h
S Slave Address A Select Address
(Ex.)
80h
20h
A Data
A Data
00h
00h
: Master to Slave
A Data
00h
: Slave to Master
AP
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2012.03 - Rev.A