BD9406KS2 Datasheet, PDF (15/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
Technical Note
3. S-P Conversion 1 and S-P Conversion 2
BU9406KS2 has two built-in serial-parallel conversion circuits. (S-P Conversion 1 and S-P Conversion 2)
S-P conversions 1 and 2 are blocks which receive 3-line serial input audio data from pins and convert it to parallel data.
Input from DATAI1, BCKI1 and LRCKI1 (pins 52,53 and 54), DATAI2, BCKI2 and LRCKI2 (pins 55, 56, and 57), DATAI3,
BCKI3 and LRCKI3 (pins 58, 63 and 64), and DATAI4, BCKI4 and LRCKI4 (pins 65, 66 and 67) are selected.
The three input formats are IIS, left-justified and right-justified. The bit clock frequency may be selected from either 64fs or
48fs, but when 48fs is selected, the input format is always right-justified. 16bit, 20bit and 24bit output may be selected for
each format.
Below are the timing charts for each transfer format.
IIS Format
LRCKI
BCKI
DATAI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
Left-Justified Format
LRCKI
BCKI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
DATAI S
S
16bit
20bit
24bit
16bit
20bit
24bit
Right-Justified Format
LRCKI
BCKI
DATAI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
48fs
LRCKO
BCKO
DATAO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
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2012.03 - Rev.A