BD9406KS2 Datasheet, PDF (28/38 Pages) Rohm – 28bit Audio DSP with Built-in 2ch ADC, 6ch DAC and ASRC

BU9406KS2
Technical Note
5. P-S Conversion 1 and P-S Conversion 2
BU9406KS2 has two built-in parallel-serial conversion circuits (P-S Conversion 1 and P-S Conversion 2). P-S conversion 1
converts the output from the AD converter or ASRC to 3-line serial data before sending it from DATAOA, BCKOA and
LRCKOA (pins 48, 49 and 51) or DATAOB, BCKOB and LRCKOB (pins 45, 46 and 47). (Refer to &h08[6:4] and &h08[2:0])
P-S conversion 2 converts the ASRC or DSP output into 3-line serial data before transmitting it from DATAOC, BCKOC and
LRCKOC (pins 42, 43 and 44).
The system clock for P-S conversion 1 is configured at &h0A[5:4], however, when outputting an AD converter, SYSCLK
should be selected. When outputting ASRC, the same selection should be made as with &h0A[1:0].
The three output formats are IIS, left-justified and right-justified. 16bit, 20bit and 24bit output can be selected for each
format.
The timing charts for each transfer format are as follows:
IIS_IISF_Fo_or_rm_ma_att
LRCKO
BCKO
DATAO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
Left-Justified Format
LRCKO
BCKO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
DATAO S
S
16bit
20bit
24bit
16bit
20bit
24bit
Right-Justified Format
LRCKO
BCKO
DATAO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MSB
LSB
MSB
LSB
S
S
16bit
20bit
24bit
16bit
20bit
24bit
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2012.03 - Rev.A