RXC101 Datasheet, PDF (26/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

Data Rate Setup Register [POR=C823h]
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
1
1
0
0
1
0
0
0 PRE BITR6 BITR5 BITR4 BITR3 BITR2 BITR1 BITR0
The Data Rate Setup Register configures:
• the expected data rate for the receiver
• the prescaler
• the effects of the data rate on clock recovery
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Data Rate Setup Register.
Bit [7] – Prescaler Enable: When set this bit enables the prescaler to obtain smaller values of expected
data rates. The prescaler value is approximately 1/8.
Bit [6..0] – Data Rate Parameter Value: These bits represent the decimal value of the 7-bit parameter
used to calculate the expected data rate. To calculate the expected data rate, use the following
formula:
DRexp(kbps) = 10000 / [29 * (BITR[6..0]+1) * (1+PRE*7)]
where BITR[6..0] is the decimal value 0 to 127 and the prescaler (PRE) is ‘1’ (on) or ‘0’ (off).
To calculate the BITR[6..0] decimal value for a given bit rate, use the following formula:
BITR[6..0] = 10000 / [29 * (1+PRE*7) * DRexp
where DRexp is the expected data rate and PRE is defined above.
Without the prescaler, the definable data rates range from 2.694kpbs to 344.828kbps. With the prescaler
enabled, the definable data rates range from 337 bps to 43.103kpbs.
The Slow clock recovery mode requires more accurate bit timing when setting the data rate. To calculate
the accuracy of the data rate for both Fast and Slow mode, use the following:
Slow mode Accuracy = ∆BR/BR < 1/(29 * N) Fast mode Accuracy = ∆BR/BR < 3/(29 * N)
where N is the longest number of expected ones or zeros in the data stream, ∆BR is the difference in the
actual data rate vs. the set data rate in the transmitter, and BR is the expected data rate as set above
using BITR[6..0].
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