RXC101 Datasheet, PDF (12/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

3. RXC101 Functional Characteristics
RF_P
RF_N
LNA
0 /9 0
FSK
I/Q
ASK
DEMOD
RSSI
VCO
PLL
/N
OSC
XTAL/REF
RSSIA
+
-
B_DA_ET_TT
VDD GND
CONTROL
LOGIC
SDI
SSDCOK/FFIT
nCS
nIRQ
DATA / nFSEL
CR/FINT/FCAP
CLKOUT
DDET
R
nRESET
Figure 5. Functional Block Diagram
Input Amplifier (LNA)
The LNA has selectable gain (0dB, -6dB, -14dB, -20dB) which may be useful in an environment with
strong interferers. The LNA has a 250ΩOhm differential input impedance (0dB, -14dB) which requires a
matching circuit when connected to 50 Ohm devices. Registers common to the LNA are:
• Power Management Register
• Receiver Control Register
Baseband Data and Filtering
The baseband receiver has several programmable options that optimize the data link for a wide range of
applications. The programmable functions include:
• Receive bandwidth
• Receive data rate
• Baseband Analog Filter
• Baseband Digital Filter
• Clock Recovery (CR)
• Receive FIFO
• Data Quality Detector
The receive bandwidth is programmable from 67 kHz to 400 kHz to accommodate various FSK
modulation deviations as well as fast data rates. If the deviation is known for a given transmitter, the best
results are obtained with a bandwidth at least twice the transmitter FSK deviation.
The receive data rate is programmable from 337bps to 344kbps. An internal prescaler is used to give
better resolution when setting up the receive data rate. The prescaler is optional and may be disabled
through the Data Rate Setup Register.
The type of baseband filtering is selectable between an Analog filter and a Digital filter. The analog filter
is a simple RC lowpass filter. An external capacitor may be chosen depending on the actual data rate.
The chip has an integrated 10KOhm resistor in series that makes the RC lowpass network. With the
analog filter selected, a maximum data rate of 256kbps can be achieved. The digital filter is used with a
clock frequency of 29X data rate. In this mode a clock recovery (CR) circuit is used to provide for a
synchronized clock source to recover the data using an external processor. The CR has three modes of
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