RXC101 Datasheet, PDF (13/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

operation: fast, slow, and automatic, all configurable through the Baseband Filter Register. The CR
circuit works by sampling the preamble on the incoming data. The preamble must contain a series of 1’s
and 0’s in order for the CR circuit to properly extract the data timing. In slow mode the CR circuit requires
more sampling (12 to 16 bits) and thus has a longer settling time before locking. In fast mode the CR
circuit takes fewer samples (6 to 8 bits) before locking so settling time is not as long and timing accuracy
is not critical. In automatic mode the CR circuit begins in fast mode to coarsely acquire the timing period
with fewer samples then changes to slow mode after locking. Further details of the CR and data rate
clock are provided in the Baseband Filter Register. CR is only used with the digital filter and data rate
clock. These are not used when configured for the analog filter.
The Data Quality Detector looks at the unfiltered incoming data and counts the “spikes” for a given period.
The higher the “spike” count, the lower the data quality. The data quality threshold may be set, restricting
when the chip may report “Good Signal Quality”.
Data Quality Detector(DQD)
The DQD is a unique function of the TRC101. The DQD circuit looks at the prefiltered incoming and
counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link.
This parameter is programmable through the Data Filter Command Register. The DQD count threshold is
programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means
the higher the content of noise spikes in the data stream the more difficult it will be to recover clock
information as well as data.
Valid Data Detector(VDI)
The VDI is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the Clock
Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The VDI
signal is valid when using either the internal receive FIFO or an external pin to capture baseband data.
The VDI has three modes of operation: slow, medium, fast. Each mode is dependent on what signals it
uses to determine valid data as well as the number of incoming preamble bits present at the beginning of
the packet.
Receiver FIFO
The receive FIFO is configured as one 16-bit register. The FIFO can be configured to generate an
interrupt after a predefined number of bits have been received. This threshold is programmable from 1 to
15 bits. It is recommended to set the threshold to at least half the length of the register (8 bits) to insure
the external host processor has time to set up.
The receive FIFO may also be configured to fill only when valid data has been identified. The RXC101
has a synchronous pattern detector that watches incoming data for a particular pattern. When it sees this
pattern it begins to store any data that follows. At the same time, if pin 16 is configured for Valid Data
Indicator output (See Receiver Control Register), this pin will go ‘high’ signaling valid data. This can be
used to prepare a host processor for retrieving data. The internal synchronous pattern is set to 2DD4h
and is not configurable.
The FIFO can be read out through the SDO pin only by toggling the nFSEL pin (6) which selects the FIFO
for read and reading out data on the next clock. The FINT pin (7) will stay active (logic ‘1’) until the last bit
has been read out, and it will then go ‘low’. This pin may also be polled to watch for valid data. When the
number of bits received in the FIFO match the pre-programmed limit, this pin will go active (logic ‘1’) and
stay active until the last bit is read out as above. An alternative method of reading the FIFO is through an
SPI bus Status Register read. The drawback to this is that all interrupt and status bits must be read first
before the FIFO bits appear on the bus. This could pose a problem for receiving large amounts of data.
The best method is using the SDO pin and the associated FIFO function pins.
Receive Signal Strength Indicator (RSSI)
The RXC101 provides an analog RSSI and a digital RSSI. The digital RSSI threshold is programmable
through the Receiver Control Register and is readable through the Status Register only. When an
incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the Status Register
is set.
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