RXC101 Datasheet, PDF (16/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

4. Control and Configuration Registers
Status Register (Read Only)
Bit
15
FIFOIT
Bit
14
FIFOV
Bit
13
WKINT
Bit Bit Bit Bit
12 11 10 9
LB FIFEMP RSSI GDQD
Bit
8
CRLCK
Bit Bit
7
6
AFATGL AFA
Bit
5
OFFSGN
Bit
4
OFF4
Bit
3
OFF3
Bit
2
OFF2
Bit
1
OFF1
Bit
0
OFF0
The Status Register provides feedback for:
• FIFO overwrite
• FIFO fill interrupt
• Low Battery
• Data Quality
• Digital RSSI signal level
• Clock Recovery
• Frequency Offset value and sign
• AFA
Note: The Status Register read command begins with a logic ‘0’ where all other register commands begin
with a logic ‘1’.
Bit [15]:FIFOIT – When set, indicates that the number of data bits received by the FIFO has reached it
programmed limit. See FIFO Fill Bit Count Bits[7..4] of the FIFO Configuration
Register.
Bit [14]:FIFOV – When set, indicates receive FIFO overflow. (Cleared after Status Reg read).
Bit [13]:WKINT – When set, indicates a Wake-up timer overflow. (Cleared after Status Reg read).
Bit [12]:LB – When set, indicates the supply voltage is below the preprogrammed limit. See Battery
Detect Threshold and Clock Output Register.
Bit [11]:FIFEMP – When set, indicates receive FIFO is empty.
Bit [10]:RSSI – When set, this bit indicates that the incoming RF signal is above the preprogrammed
Digital RSSI limit.
Bit [9]:GDQD – When set, indicates good data quality.
Bit [8]:CRLCK – When set, indicates Clock Recovery is locked.
Bit [7]:AFATGL – For each AFA cycle run, this bit will toggle between logic ‘1’ and logic ‘0’.
Bit [6]:AFA – When set, indicates that the frequency adjust has detected the same offset value for two
consecutive measurements and thus the frequency is stabilized.
Bit [5]:OFFSGN – Indicates the difference in frequency is higher (logic ‘1’) or lower (logic ‘0’) than the chip
frequency.
Bit [4..0]:OFF[4..0] – The offset value to be added to the frequency control word (internal PLL).
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