RXC101 Datasheet, PDF (18/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

Configuration Register (continued)
Bit [3..1] – Receiver Baseband Bandwidth: These bits set the baseband bandwidth of the demodulated
data. The bandwidth can accommodate different FSK deviations and data rates. See Table 6 for
bandwidth configuration.
Table 6.
Baseband BW (kHz) BB2 BB1 BB0
Resvd
000
400
001
340
010
270
011
200
100
134
101
67
110
Resvd
111
Bit [0] – Clock Output Disable: This bit disables the oscillator clock output when set. On chip reset or
power up, clock output is on so that a processor may begin execution of any special setup
sequences as required by the designer. See Battery Detect Threshold and Clock Output Register
section for programming details.
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