RXC101 Datasheet, PDF (10/33 Pages) RF Monolithics, Inc – Multi-channel High data rate Programmable

At power-up the chip samples the state of pin 8. If the pin is logic ‘1’ then it enters simple mode. If pin 8
is GND or left unconnected it enters processor mode. In simple mode, 6 pins select the band and
frequency within that band of operation. A seventh pin is available to operate the chip in duty cycle mode.
Table 2 shows the 6-pin setup configuration.
Table 2.
315MHz
BS[1,0]=00
433MHz
BS[1,0]=01
868MHz
BS[1,0]=10
916MHz
BS[1,0]=11
Address
FS3
FS2
FS1
FS0
310.320 4330360 *867.680 *900.960 D4h
0000
310.960 433.440 *867.840 902.880
D2h
0001
311.600 433.520 *868.000 904.800
B4h
0010
312.240 433.600 868.160 906.720
B2h
0011
312.880 433.680 868.320 908.640
D4h
0100
313.520 433.760 868.480 910.560
D2h
0101
314.160 433.840 868.640 912.480
B4h
0110
314.800 433.920 868.800 914.400
B2h
0111
315.440 434.000 868.960 916.320
D4h
1000
316.080 434.080 869.120 918.240
D2h
1001
316.720 434.160 869.280 920.160
B4h
1010
317.360 434.240 869.440 922.080
B2h
1011
318.000 434.320 869.600 924.000
D4h
1100
318.640 434.400 869.760 925.920
D2h
1101
319.280 434.480 869.920 927.840
B4h
1110
319.920 434.560 *870.080 *929.760
B2h
1111
*Out of Band Frequencies
NOTE: Setting FS0=’1’ will change the DRSSI threshold from -103dBm to -97dBm.
For simple mode a predefined data sequence is defined in order to toggle the four outputs available. The
sequence includes a 16-bit preamble, synch word, address, and control bytes. The following is the
sequence flow:
Preamble (AAh)
Synch Word (2Dh)
Address (D4h, etc..)
Output Control Byte
Output Control Byte
1’s Complement
Output Control Byte
(Transmit Order)
DO3
CB(1)
DO3
CB(0)
DO2
CB(1)
DO2
CB(0)
DO1
CB(1)
(Transmit Order)
DO1
CB(0)
DO0
CB(1)
DO0
CB(0)
10