H8SX1648 Datasheet, PDF (993/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransfer frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1) th
transfer frame
Ds D0 D1 D2 D3 D4
TDRE
TEND
FER/ERS
Transfer from TDR to TSR
Transfer from TDR to TSR
[2]
Transfer from TDR to TSR
[4]
[1]
[3]
Figure 19.29 Data Re-Transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR.
Figure 19.30 shows the TEND flag set timing.
I/O data
TXI
(TEND interrupt)
GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Guard time
12.5 etu
GM = 1
[Legend]
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
11.0 etu
Figure 19.30 TEND Flag Set Timing during Transmission
Rev. 2.00 Jul. 31, 2008 Page 963 of 1438
REJ09B0365-0200