H8SX1648 Datasheet, PDF (322/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 Bus Controller (BSC)
9.10.8 Controlling Precharge Cycle
The number of precharge cycles (Tp) can be selected from one to four clock cycles by bits TPC1
and TPC0 in DRACCR. Set the bit according to the DRAM to be used and the frequency of this
LSI so that the number of precharge cycle can be optimal.
Figure 9.42 shows an access timing example when two Tp cycles are specified.
The setting of bits TPC1 and TPC0 affect the Tp cycle of a refresh cycle.
Bφ
Address bus
RAS
LUCAS
LLCAS
Read
WE
OE (RD)
Data bus
Write
WE
OE (RD)
Data bus
BS
RD/WR
T_p1
T_p2
T_r
T_c1
T_c2
Row address
Column address
High
High
Figure 9.42 Access Timing Example of Two Precharge Cycles (RAST = 0 and CAST = 0)
Rev. 2.00 Jul. 31, 2008 Page 292 of 1438
REJ09B0365-0200