H8SX1648 Datasheet, PDF (349/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 Bus Controller (BSC)
9.11.7 Controlling Row Address Output Cycle
When the time between the ACTV command and the subsequent READ or WRIT command does
not meet a given specification, the Trw cycle in which the NOP command is output can be
inserted for one to three cycles between the Tr cycle in which the ACTV command is output and
the Tc1 cycle in which the column address is output. Set the bit according to the SDRAM to be
used and the frequency of this LSI so that the number of wait cycles can be optimal.
Figures 9.63 and 9.64 show a timing example when the one Trw cycle is inserted.
SDRAMφ
Address bus
Precharge-sel
CS
RAS
CAS
WE
CKE
T_p
T_r
T_rw
T_c1
T_cl
T_c2
Row address
Row
address
Column address
High
DQMLU
DQMLL
D15 to D8
D7 to D0
BS
RD/WR
PALL ACTV NOP
READ
NOP
Figure 9.63 Read Timing Example of Row Address Output Retained for 1 Clock Cycle
(RCD1 = 0, RCD0 = 1, CAS Latency = 2)
Rev. 2.00 Jul. 31, 2008 Page 319 of 1438
REJ09B0365-0200