H8SX1648 Datasheet, PDF (817/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.5 Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 14.48 shows the timing in this case.
Pφ
Address
TCNT write cycle
T₁
T₂
TCNT address
Write
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 14.48 Conflict between TCNT Write and Increment Operations
14.10.6 Conflict between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 14.49 shows the timing in this case.
Pφ
Address
TGR write cycle
T₁
T₂
TGR address
Write
Compare match
signal
TCNT
Disabled
N
N+1
TGR
N
M
TGR write data
Figure 14.49 Conflict between TGR Write and Compare Match
Rev. 2.00 Jul. 31, 2008 Page 787 of 1438
REJ09B0365-0200