H8SX1648 Datasheet, PDF (882/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 16 8-Bit Timers (TMR)
16.5.2 Timing of CMFA and CMFB Setting at Compare Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT
values match, the compare match signal is not generated until the next TCNT clock input. Figure
16.9 shows this timing.
Pφ
TCNT
N
TCOR
N
Compare match
signal
N+1
CMF
Figure 16.9 Timing of CMF Setting at Compare Match
16.5.3 Timing of Timer Output at Compare Match
When a compare match signal is generated, the timer output changes as specified by the bits OS3
to OS0 in TCSR. Figure 16.10 shows the timing when the timer output is toggled by the compare
match A signal.
Pφ
Compare match A
signal
Timer output pin
Figure 16.10 Timing of Toggled Timer Output at Compare Match A
Rev. 2.00 Jul. 31, 2008 Page 852 of 1438
REJ09B0365-0200