H8SX1648 Datasheet, PDF (884/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 16 8-Bit Timers (TMR)
16.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure
16.14 shows the timing of this operation.
Pφ
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 16.14 Timing of OVF Setting
16.6 Operation with Cascaded Connection
If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode).
16.6.1 16-Bit Counter Mode
When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
(1) Setting of Compare Match Flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
(2) Counter Clear Specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by
the TMRI0 pin has been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
Rev. 2.00 Jul. 31, 2008 Page 854 of 1438
REJ09B0365-0200