H8SX1648 Datasheet, PDF (477/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 DMA Controller (DMAC)
10.5.11 Bus Cycles in Single Address Mode
(1) Single Address Mode (Read and Cycle Stealing)
In single address mode, one byte, one word, or one longword of data is transferred at a single
transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the
CPU or DTC are executed in the bus released cycles.
In figure 10.34, the TEND signal output is enabled and data is transferred in bytes from the
external 8-bit 2-state access space to the external device in single address mode (read).
Bφ
Address bus
RD
DMA read
cycle
DMA read
cycle
DMA read
cycle
DMA read
cycle
DACK
TEND
Bus
released
Bus
released
Bus
released
Bus Last transfer Bus
released cycle released
Figure 10.34 Example of Transfer in Single Address Mode (Byte Read)
Rev. 2.00 Jul. 31, 2008 Page 447 of 1438
REJ09B0365-0200