H8SX1648 Datasheet, PDF (745/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.1 Timer Control Register (TCR)
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one
for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit
Bit Name
Initial Value
R/W
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
CCLR2 0
R/W Counter Clear 2 to 0
6
CCLR1 0
5
CCLR0 0
R/W These bits select the TCNT counter clearing source. See
R/W ^{tables 12.4 and 12.5 for details.}
4
CKEG1 0
R/W Clock Edge 1 and 0
3
CKEG0 0
R/W These bits select the input clock edge. For details, see
table 14.6. When the input clock is counted using both
edges, the input clock period is halved (e.g. Pφ/4 both
edges = Pφ/2 rising edge). If phase counting mode is
used on channels 1, 2, 4, and 5, this setting is ignored
and the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is Pφ/4
or slower. This setting is ignored if the input clock is Pφ/1,
or when overflow/underflow of another channel is
selected.
2
TPSC2 0
R/W Timer Prescaler 2 to 0
1
TPSC1 0
0
TPSC0 0
R/W These bits select the TCNT counter clock. The clock
R/W ^{source can be selected independently for each channel.}
See tables 12.7 to 12.12 for details. To select the external
clock as the clock source, the DDR bit and ICR bit for the
corresponding pin should be set to 0 and 1, respectively.
For details, see section 13, I/O Ports.
Rev. 2.00 Jul. 31, 2008 Page 715 of 1438
REJ09B0365-0200