H8SX1648 Datasheet, PDF (305/1472 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 9 Bus Controller (BSC)
9.9 Address/Data Multiplexed I/O Interface
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this
LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed
I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly
to this LSI.
9.9.1 Address/Data Multiplexed I/O Space Setting
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be
specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in
MPXCR.
9.9.2 Address/Data Multiplex
In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 9.18
shows the relationship between the bus width and address output.
Table 9.18 Address/Data Multiplex
Bus Width Cycle
8 bits
Address
Data Pins
PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
- - - - - - - - A7 A6 A5 A4 A3 A2 A1 A0
Data
- - - - - - - - D7 D6 D5 D4 D3 D2 D1 D0
16 bits Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
9.9.3 Data Bus
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.
For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,
D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is
accessed, the corresponding address will be output to the address bus.
For details on access size and data alignment, see section 9.5.6, Endian and Data Alignment.
Rev. 2.00 Jul. 31, 2008 Page 275 of 1438
REJ09B0365-0200