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M16C62A Datasheet, PDF (96/242 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register 2 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Bit
symbol
Bit name
IICM2 I2C mode select bit 2
Function
(I2C bus exclusive use)
Refer to Table 1.14.11
CSC Clock-synchronous bit
SWC SCL wait output bit
ALS
SDA output stop bit
STAC UART2 initialization bit
SWC2 SCL wait output bit 2
SDHI SDA output disable bit
SHTC Start/stop condition
control bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
1 : Set this bit to “1” in I2C mode
(refer to Table 1.14.12)
RW
UART2 special mode register 3 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
When reset
Indeterminate
(However, when SDDS = “1”, the initial value is “0016”)
Bit
symbol
Bit name
Function
(I 2C bus exclusive use register)
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
DL0
SDA digital delay setup b7 b6 b5
bit
0 0 0 : Analog delay is selected
(Note 1, Note 2, Note 3, 0 0 1 : 1 to 2 cycle(s) of 1/f(XIN)
DL1
Note 4)
0 1 0 : 2 to 3 cycles of 1/f(XIN)
0 1 1 : 3 to 4 cycles of 1/f(XIN)
Digital delay
1 0 0 : 4 to 5 cycles of 1/f(XIN)
is selected
DL2
1 0 1 : 5 to 6 cycles of 1/f(XIN)
1 1 0 : 6 to 7 cycles of 1/f(XIN)
1 1 1 : 7 to 8 cycles of 1/f(XIN)
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset,
these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be
read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,
only the digital delay value is effective.
Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 100 ns, so be sure to take this into account when using the device.
Figure 1.14.9. Serial I/O-related registers (6)
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