M16C62A Datasheet, PDF (125/242 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3, 4
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
SiC 036216, 036616
4016
Bit
symbol
Bit name
Description
RW
SMi0
SMi1
Internal synchronous
clock select bit
b1 b0
0 0 : Selecting f1
0 1 : Selecting f8
1 0 : Selecting f32
1 1 : Must not be set.
SMi2 SOUTi output disable bit
0 : SOUTi output
1 : SOUTi output disable(high impedance)
SMi3 S I/Oi port select bit
(Note 2)
0 : Input-output port
1 : SOUTi output, CLK function
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
SMi5 Transfer direction select 0 : LSB first
bit
1 : MSB first
SMi6 Synchronous clock
select bit (Note 2)
0 : External clock
1 : Internal clock
SMi7 SOUTi initial value
Effective when SMi3 = 0
set bit
0 : L output
1 : H output
Note 1: Set “1” in bit 2 of the protection register (000A16) in advance to write to the
S I/Oi control register (i = 3, 4).
Note 2: When using the port as an input/output port by setting the SI/Oi port
select bit (i = 3, 4) to “0”, be sure to set the sync clock select bit to “1”.
SI/Oi bit rate generator (Note 1, 2)
b7
b0
Symbol
S3BRG
S4BRG
Address
036316
036716
When reset
Indeterminate
Indeterminate
Indeterminate
Assuming that set value = n, BRGi divides the count
source by n + 1
Values that can be set R W
0016 to FF16
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (Note 1, 2)
b7
b0
Symbol
S3TRR
S4TRR
Address
036016
036416
When reset
Indeterminate
Indeterminate
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Note 1: SI/O3 is exclusive to transmission.
Note 2: Write a value to this register while transmit/receive halts.
RW
Figure 1.14.31. S I/O3, 4 related register
124