M16C62A Datasheet, PDF (113/242 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock asynchronous serial I/O (UART) mode
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock
Transmit enable ^{“1”}
bit(TE)
“0”
Transmit buffer
“1”
empty flag(TI)
“0”
TxD2
RxD2
Signal conductor level
(Note 2)
Transmit register “1”
empty flag (TXEPT)
“0”
Transmit interrupt ^{“1”}
request bit (IR)
“0”
Data is set in UART2 transmit buffer register
Note 1
Start
bit
Transferred from UART2 transmit buffer register to UART2 transmit register
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
An “L” level returns from TxD2 due to
the occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
The level is detected by the
interrupt routine.
The level is
detected by the
interrupt routine.
Shown in ( ) are bit symbols.
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Tc
Transfer clock
Receive enable
“1”
bit (RE)
“0”
RxD2
TxD2
Signal conductor level
(Note 2)
Receive complete “1”
flag (RI)
“0”
Receive interrupt ^{“1”}
request bit (IR)
“0”
Start
bit
Parity Stop
bit
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
An “L” level returns from TxD2 due to
the occurrence of a parity error.
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Read to receive buffer
Read to receive buffer
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f1, f8, f32)
n : value set to BRG2
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.14.21. Typical transmit/receive timing in UART mode (used for the SIM interface)
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