|
M16C62A Datasheet, PDF (101/242 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER | |||
|
◁ |
Clock synchronous serial I/O mode
Mitsubishi microcomputers
M16C / 62A Group (80-pin)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
⢠Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
â1â
Transmit enable
bit (TE)
â0â
Transmit buffer â1â
empty flag (Tl)
â0â
âHâ
CTSi
âLâ
CLKi
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
TCLK
Stopped pulsing because CTS = âHâ
Stopped pulsing because transfer enable bit = â0â
TxDi
Transmit
â1â
register empty
flag (TXEPT)
â0â
Transmit interrupt â1â
request bit (IR) â0â
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Shown in ( ) are bit symbols.
Cleared to â0â when interrupt request is accepted, or cleared by software
The above timing applies to the following settings:
⢠Internal clock is selected.
⢠CTS function is selected.
⢠CLK polarity select bit = â0â.
⢠Transmit interrupt cause select bit = â0â.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32)
n: value set to BRGi
⢠Example of receive timing (when external clock is selected)
â1â
Receive enable
bit (RE)
â0â
â1â
Transmit enable
bit (TE)
â0â
Transmit buffer â1â
empty flag (Tl) â0â
âHâ
RTSi
âLâ
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Transferred from UARTi receive register
Receive complete â1â
to UARTi receive buffer register
flag (Rl)
â0â
Read out from UARTi receive buffer register
Receive interrupt â1â
request bit (IR) â0â
Cleared to â0â when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
⢠External clock is selected.
⢠RTS function is selected.
⢠CLK polarity select bit = â0â.
fEXT: frequency of external clock
Meet the following conditions are met when the CLK
input before data reception = âHâ
⢠Transmit enable bit â1â
⢠Receive enable bit â1â
⢠Dummy data write to UARTi transmit buffer register
Figure 1.14.11. Typical transmit/receive timings in clock synchronous serial I/O mode
100
|
▷ |