7643_06 Datasheet, PDF (93/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
OVERVIEW
FLASH MEMORY MODE
Software Commands (CPU Rewrite Mode)
Table 10 lists the software commands.
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
qRead Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (DB0 to DB7).
The read array mode is retained intact until another command is
written.
qRead Status Register Command (7016)
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (DB0 to DB7) by a read in the
second bus cycle.
The status register is explained in the next section.
qClear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
qProgram Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (DB0 to DB7). The status
register bit 7 (SR7) is set to “0” at the same time the write opera-
tion starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains ac-
tive until the next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
Start
Write 4016
Write ^{Write address}
Write data
Status register
read
SR7 = 1 ?
or
NO
RY/BY = 1 ?
YES
SR4 = 0 ?
NO
Program
error
YES
Program
completed
Table 10 List of software commands (CPU rewrite mode)
Command
Read array
Read status register
Clear status register
Cycle number
1
2
1
Mode
Write
Write
Write
Fig. 74 Program flowchart
First bus cycle
Address
Data
(DB0 to DB7)
X ^{(Note 4)}
F F1 6
X
7016
X
5016
Second bus cycle
Mode
Address
Data
(DB0 to DB7)
Read
X
SRD ^{(Note 1)}
Program
2
Write
X
4016
Write WA ^{(Note 2)} WD ^{(Note 2)}
Erase all blocks
2
Write
X
2016 Write
X
2016
Block erase
2
Write
X
2016
Write BA ^{(Note 3)}
D016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
Rev.2.00 Aug 28, 2006 page 76 of 103
REJ09B0133-0200