7643_06 Datasheet, PDF (185/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
APPLICATION
2.4 UART
RESET
Initialization
..... _{(Interrupt disabled)}
CCR (Address : 1F16)
FSM1 (Address : 6D16)
FSM2 (Address : 6E16)
FSD (Address : 6F16)
FSC (Address : 6C16)
USBC (Address : 1316)
USBFIFOMR (Address : 5F16)
USBIE1 (Address : 5416)
USBINDEX (Address : 5816)
OUT_MAXP (Address : 5C16)
OUT_CSR (Address : 5A16)
UBRG (Address : 3116)
UMOD (Address : 3016)
UCON (Address : 3316)
8016
0016
FF16
0016
4116
101100x02
xxxxxx002
xxxx10012
000000012
0816
000100012
4D16
010x00002
0011x0002
DMAIS (Address : 3F16)
DMA0SL (Address : 4216)
DMA0SH (Address : 4316)
DMA0DL (Address : 4416)
DMA0DH (Address : 4516)
DMA0CL (Address : 4616)
DMA0CH (Address : 4716)
DMA0M1 (Address : 4016)
DMA0M2 (Address : 4116)
ICONA (Address : 0516)
IREQA (Address : 0216)
..... _{(interrupt enabled)}
0xxxxxxx2
6116
0016
3416
0016
6416
0016
00110x0x2
0x0x00102
0xx1xxx12
0016
Fig. 2.4.28 Control procedure (1)
q x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Refer to the USB initiral setting.
• USB initializing
Endpoint1FIFO : OUT128 bytes
Endpoint0, Endpoint1OUT interrupt enabled
Max. packet size : 64 bytes
...
• UART initializing
φ as UART clock, 1 stop bit,
Parity checking disabled, 8-bit character length
CTS function enabled, RTS function disabled
Tramsmit interrupt source : Transmit shift completed
• DMA initializing
DMA0 selected
Source address : USBFIFO1
Destination address : UART transmit buffer register 1
Transmit byte : 64 bytes fixed
DMAC channel 0 source increment : disabled
DMAC channel 0 source register increment : disabled
DMAC channel 0 destination register increment : disabled
DMAC channel 0 write control : Writing data in reload latch only
DMAC count register underflow : enabled
DMAC channel 0 transfer mode : cycle steal transfer mode
DMAC channel 0 hardware transfer request : UART transmit interrupt
DMAC channel 0 : disabled
• Others
USB function interrupt : enabled
DMAC0 interrupt : enabled
UART transmit interrupt : disabled
Rev.2.00 Aug 28, 2006 page 64 of 202
REJ09B0133-0200