7643_06 Datasheet, PDF (322/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
APPLICATION
2.10 Clock generating circuit
Control procedure: Set the relevant registers in the order shown below to prepare for a power
failure.
RESET
Initialization
CPMA (address 0016)
CCR (address 1F16)
T1 (address 2416)
T123M (address 2916)
IREQB (address 3C16), bit 7, bit 6
Base counter (internal RAM)
1 second counter (internal RAM)
ICONB (address 0616), bit 6
CLI
qX: This bit is not used here. Set it to “0” or “1” arbitrarily.
00011XXX2
1XX000002
FE16
0XX0X00X2
0,0
F516
1816
1
When selecting main clock f(XIN) (high-speed mode)
Setting for making base and one second counters activate during
timer 1 interrupt
In the normal power state, these software counters generate one
second.
N
Detect power failure ?
Y
T123M (address 2916), bit 2
ICONB (address 0616), bit 6
CPMA (address 0016), bit 7
CPMA (address 0016), bit 5
IREQB (address 0616), bit 7, bit 6
T1 (address 2416)
T2 (address 2516)
1
0
1 (Note)
1 (Note)
0, 0
0216
E216
Timer 1 count source: f(XCIN)
Timer 1 interrupt: Disabled
Internal system clock: f(XCIN) (low-speed mode)
Main clock f(XIN): Oscillation stopped
Setting for generating timer 2 interrupt every second
Generation of one second by hardware timer during
power failure
ICONB (address 0616), bit 7
1
Execute WIT instruction
N
Return condition for power failure is
satisfied ?
Y
Return processing from power failure
Timer 2 interrupt: Enabled
Timer 2 interrupt occurs every second
(return from wait mode)
Note: Do not switch at one time.
Fig. 2.10.15 Control procedure (1)
Rev.2.00 Aug 28, 2006 page 201 of 202
REJ09B0133-0200