7643_06 Datasheet, PDF (404/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
APPENDIX
3.5 Control registers
ROM code protect control register
b7 b6 b5 b4 b3 b2 b1 b0
11
ROM code protect control register
(ROMCP : address FFC916) (Note 1)
b
Name
Functions
At reset R W
0 Reserved bits.
Indefinite at read. Write “0” at write.
1
1
1
2 ^{ROM code protect level 2 b3b2}
1
set bits (ROMCP2)
0 0 : Protect enabled
3 ^{(Notes 2, 3)}
0 1 : Protect enabled
1 0 : Protect enabled
1
1 1 : Protect disabled
4 ^{ROM code protect reset b5b4}
1
bits (ROMCR) (Note 4)
0 0 : Protect removed
0 1 : Protect set bits effective
5
1 0 : Protect set bits effective
1
1 1 : Protect set bits effective
6 ^{ROM code protect level 1 b7b6}
1
set bits (ROMCP1)
0 0 : Protect enabled
(Note 2)
0 1 : Protect enabled
7
1 0 : Protect enabled
1
1 1 : Protect disabled
Notes 1: This area is on the ROM in the mask ROM version.
2: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
Fig. 3.5.55 Structure of ROM code protect control register
Rev.2.00 Aug 28, 2006 page 81 of 98
REJ09B0133-0200