7643_06 Datasheet, PDF (76/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
OVERVIEW
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 20 cycles or more of φ. Then the RESET pin is returned to
an “H” level, and reset is released. They must be performed when
the power source voltages are between 3.00 V and 3.60 V or 4.15
V and 5.25 V.
After the reset is completed, the program starts from the address
contained in address FFFA16 (high-order byte) and address
FFFB16 (low-order byte).
After oscillation has restarted, the timers 1 and 2 secures waiting
time for the internal clock φ oscillation stabilized automatically by
setting the timer 1 to “FF16” and timer 2 to “0116”. The internal
clock φ retains “H” level until Timer 2’s underflow and it cannot be
supplied until the underflow.
The pins state during reset are follows:
•When CNVss = “H”
Ports P0, P1, P33 to P37
: Outputting
Pins other than above mentioned ports : Inputting
•When CNVss = “L”
All pins
: Inputting.
RESET
Poweron
Power source
VCC voltage
0V
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc = 3.00 or 4.15 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 53 Reset circuit example
φ
RESET
Internal
reset
Address
Data
SYNC
?
?
?
?
FFFA FFFB ^ADH,L
Reset address from
the vector table.
?
?
?
?
ADL
ADH
XIN: 512 clock cycles
Notes: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 54 Reset sequence
Rev.2.00 Aug 28, 2006 page 59 of 103
REJ09B0133-0200