7643_06 Datasheet, PDF (27/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
OVERVIEW
FUNCTIONAL DESCRIPTION
On-going Routine
Push return address
on stack
Interrupt request
(Note)
M (S) (PCH)
Execute JSR
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
POP return
address from stack
Execute RTS
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
Push return address
on stack
(S) (S) – 1
M (S) (PS)
Push contents of processor
status register on stack
(S) (S) – 1
Interrupt
Service Routine
Execute RTI
I Flag is set from “0” to “1”
Fetch the jump vector
(S)
(PS)
(S) + 1
M (S)
POP contents of
processor status
register from stack
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
POP return
address
from stack
(PCH) M (S)
Note: Condition for acceptance of an interrupt Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Accumulator
Processor status register
PHA
PHP
Pop instruction from stack
PLA
PLP
Rev.2.00 Aug 28, 2006 page 10 of 103
REJ09B0133-0200