7643_06 Datasheet, PDF (67/424 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

7643 Group
OVERVIEW
FUNCTIONAL DESCRIPTION
b7
b0
0 1 ✕ 0 0 ✕ ✕ ^{USB interrupt enable register 2 (address 005516)}
USBIE2
Reserved bit (Undefined at read/“0” at write)
Reserved bit (“0” at read/write)
Reserved bit (Undefined at read/“0” at write)
Reserved bit (“1” at read/write)
Reserved bit (“0” at read/write)
USB suspend/resume interrupt enable bit (INTEN15)
0: Disabled
1: Enabled
Fig. 41 Structure of USB interrupt enable register 2
[USB Endpoint Index Register] USBINDEX
This register specifies the accessible endpoint. It serves as an in-
dex to endpoint-specific USB Endpoint x IN Control Register, USB
Endpoint x OUT Control Register, USB Endpoint x IN Max. Packet
Size Register, USB Endpoint x OUT Max. Packet Size Register,
USB Endpoint x OUT Write Count Register, and USB FIFO Mode
Selection Register (x = 0 to 2).
b7
00000
b0
USB endpoint index register (address 005816)
USBINDEX
Endpoint index bit (EPINDEX) (Note)
b2b1b0
0 0 0: Endpoint 0
0 0 1: Endpoint 1
0 1 0: Endpoint 2
0 1 1: Not used
1 0 0: Not used
1 0 1: Not used
1 1 0: Not used
1 1 1: Not used
Reserved bit (“0” at read/write)
Note: Do not set Endpoint except Endpoint 0, 1 and 2.
Fig. 42 Structure of USB frame number registers
Rev.2.00 Aug 28, 2006 page 50 of 103
REJ09B0133-0200