SH7137_09 Datasheet, PDF (9/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
3. Changes to PWM Duty Cycle
Figure 7 shows the timing of updating values for the PWM duty cycle. In this sample program, the register settings
for PWM duty cycle are incremented or decremented from the handler for a compare-match interrupt with TGRA_3
(that generated at the highest counter value). Changes to three buffer registers TGRD_3, TGRC_4, and TGRD_4 are
used to increment or decrement the values of PWM duty cycle. When the duty cycle is changed, make sure that the
last setting to be made is that for TRGR_4. Furthermore, if the value in TGRD_4 is neither incremented nor
decremented, make sure that a value is written to TGRD_4 after the registers with values to be incremented or
decremented have been updated.
TCNT_3 and TCNT_4
TGRA_3
TCDR
TGRD_3
TGRB_3
TCNT_3
TCNTS
TCNT_4
: TGRD_3 (buffer register)
: temp (temporary register for TGRB_3)
: TGRB_3 (comparison register)
: Comparison register of TGRB_3
TDDR
H'0000
TGRA_3
interrupt flag
TGRA_3 interrupt
processing
(data update)
TGRD_3
buffer register
Temporary register
TGRB_3
compare register
*: mode
PWM mode 3 (transfer at crest and trough)
data 1
data 1
data 1
Incrementation/decrementation
of register value (data 2)
data 2
data 2
(data 2)
(data 1)
data 2
Incrementation/decrementation
of register value (data 3)
data 3
data 3
(data 3)
(data 2)
data 3
Figure 7 Timing of Updating the PWM Duty Cycle
4. Output Toggling in Synchronization with the PWM Cycle
Figure 8 shows the operations for toggling of an output level in synchronization with the PWM cycle. The PSYE bit
in the timer output control register (TOCR) is set to 1 to select toggling of an output in synchronization with the
PWM carrier cycle. Toggling is of the signal on the TIOC3A pin. The initial value for output is 1.
TCNT_3 and TCNT_4
TGRA_3
TCDR
TCNT_3
Output level is toggled on
a compare match with H'0000.
TDDR
H'0000
TIOC3A pin 1
(toggled output) 0
TCNT_4
Carrier cycle
Output level is toggled on
a compare match with H'0000.
Figure 8 Operation for Toggling an Output in Synchronization with the PWM Cycle
REJ06B0887-0100/Rev.1.00
June 2009
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