SH7137_09 Datasheet, PDF (18/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
2.5.3 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 9 gives a list of settings for registers of multi-function timer pulse unit 2 (MTU2).
Table 9 Multi-Function Timer Pulse Unit 2 (MTU2)
Register Name
Timer control register_3
(TCR_3)
Address
Setting
H'FFFFC200 H'01
Timer control register_4
(TCR_4)
H'FFFFC201 H'01
Timer counter_3 (TCNT_3) H'FFFFC210 D'40
Timer counter_4 (TCNT_4) H'FFFFC212 H'0000
Timer general register A_3
(TGRA_3)
Timer general register C_3
(TGRC_3)
H'FFFFC218
H'FFFFC224
D'2040
Timer general register B_3 H'FFFFC21A D'1020
(TGRB_3)
Timer general register D_3 H'FFFFC226
(TGRD_3)
Timer general register A_4 H'FFFFC21C D'1020
(TGRA_4)
Timer general register C_4 H'FFFFC228
(TGRC_4)
Description
Sets details of TCNT control.
• CCLR[2:0] = B'000: TCNT clearing disabled
• CKEG[1:0] = B'00: TCNT counts rising edge.
• TPSC[2:0] = B'001: TCNT counts cycles of
internal clock Pφ/4.
Sets details of TCNT control.
• CCLR[2:0] = B'000: TCNT clearing disabled
• CKEG[1:0] = B'00: TCNT counts rising edge.
• TPSC[2:0] = B'001: TCNT counts cycles of
internal clock Pφ/4.
16-bit counter
For complementary PWM mode, the initial value
is the same as the value in timer dead time data
register (TDDR).
16-bit counter
Initial value is set to H'0000.
For complementary PWM mode, sets the upper
limit (1/2 carrier cycle + dead time) of TCNT_3.
For complementary PWM mode, a buffer register
for TGRA_3.
The initial value is the same as the value in
TGRA_3.
For complementary PWM mode, a comparison
register for PWM output 1.
Determines the PWM duty cycle (initial output
value).
In complementary PWM mode, a buffer register
for TGRB_3
The initial value is the same as the value in the
TGRB_3.
Incremented or decremented value of PWM duty
cycle is set in this register
For complementary PWM mode, a comparison
register for PWM output 2.
Determines the PWM duty cycle (initial output
value).
In complementary PWM mode, a buffer register
for TGRA_4.
The initial value is the same as the value in
TGRA_4.
Incremented or decremented value of PWM duty
cycle is set in this register.
REJ06B0887-0100/Rev.1.00
June 2009
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