SH7137_09 Datasheet, PDF (15/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
2.4.3 Initialization of Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 13 shows the flow for initialization of MTU2. Settings are made to set up complementary PWM mode 3 on
channels 3 and 4.
mtu2_init()
Initialize variables
Set timer start register
(TSTR)
[1]
[1] Initialization of variables for use in setting the PWM cycle, dead time,
and PWM duty cycle
[2] Clear bits CST3 and CST4 in timer start register (TSTR)
[2]
to 0 to halt counting by the timer counters (TCNT).
Set timer control register_3 (TCR_3)
and timer control register_4 (TCR_4)
[3]
Set timer counter_3 (TCNT_3)
and timer counter_4 (TCNT_4)
[4]
[3] Specification of clock source and source for clearing
of timer counters
• CCLR[2:0] bits = B'000: Disables clearing of TCNT.
• CKEG[1:0] bits = B'00: TCNT counts rising edges.
• TPSC[2:0] bits = B'001: TCNT counts cycles of internal clock Pφ/4.
The same initial values are set in registers TCR_3 and TCR_4.
[4] Initialization of timer counters TCNT_3 and TCNT_4
• Value of dead time is set in the TCNT_3 register.
• H'0000 is set in the TCNT_4 register.
Set the following registers:
timer general register B_3 (TGRB_3),
buffer register D_3 (TGRD_3),
timer general register A_4 (TGRA_4),
[5]
buffer register C_4 (TGRC_4),
timer general register B_4 (TGRB_4),
and buffer register D_4 (TGRD_4)
Set timer general register A_3 (TGRA_3)
and timer general register C_3 (TGRC_3)
[6]
Set timer dead time data register
(TDDR)
[7]
Set timer cycle data register (TCDR)
and timer cycle buffer register (TCBR)
[8]
Set timer output control register 1
(TOCR1)
[9]
Set timer mode register_3
(TMDR_3)
[10]
Set timer output master enable register
(TOER)
[11]
Set timer interrupt enable register_3
(TIER_3)
[12]
[5] Initialization of PWM duty cycles
Initial values for PWM duty cycle are set in compare match registers
(TGRB_3, TGRA_4, and TGRB_4) and buffer registers
(TGRD_3, TGRC_4, and TGRD_4).
The same values are set in the compare match registers and buffer registers.
[6] The value (1/2 the carrier cycle + dead time) is set in the TGRA_3
register and in buffer register TGRC_3.
[7] Value of dead time is set in the dead time data register (TDDR).
[8] Half the carrier cycle is set in the timer cycle data register (TCDR)
and timer cycle buffer register (TCBR).
When the setting for non-generation of dead time has been made, set TDDR
to 1, and TGRA_3 and TGRC_3 to the value (1/2 the carrier cycle + 1).)
[9] Using the PSYE bit in timer output control register (TOCR1) to specify
enabling or disabling of output toggling in synchronization with the PWM cycle;
PWM output level setting by the OLSP and OLSN bits
• PSYE bit = B'1: Enable toggled output.
• OLSN bit = B'0: Inverse output is active at the low level.
• OLSP bit = B'0: Output of positive signals is active at the low level.
[10] Setting to complementary PWM mode 3 by timer mode register_3 (TMDR_3)
• MD[3:0] bits = B'1111: Complementary PWM mode 3 (transfer at crest and trough)
Do not make any setting in the TMDR_4 register. Additionally, mode setting
should be made while TCNT_3 and TCNT_4 are halted.
[11] Using timer output master enable register (TOER) to enable output on
PWM output pins
[12] Setting to enable or disable interrupt requests
• TGIEA bit = B'1: Enables interrupt requests (TGIA_3) from channel 3
corresponding to setting of the TGFA bit.
END
Figure 13 Initialization of MTU2
REJ06B0887-0100/Rev.1.00
June 2009
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