SH7137_09 Datasheet, PDF (19/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
Register Name
Timer general register
B_4 (TGRB_4)
Address
H'FFFFC21E
Timer general register H'FFFFC22A
D_4 (TGRD_4)
Timer dead time data H'FFFFC216
register (TDDR)
Timer cycle data
register (TCDR)
Timer cycle buffer
register (TCBR)
H'FFFFC214
H'FFFFC222
Timer output control
register 1 (TOCR1)
H'FFFFC20E
Timer mode register_3 H'FFFFC202
(TMDR_3)
Setting
D'1020
D'40
D'2000
H'40
H'3F
Description
For complementary PWM mode, a comparison register
for PWM output 3.
Determines the PWM duty cycle (initial output value).
In complementary PWM mode, a buffer register for the
TGRB_4.
The initial value is the same as the value in TGRB_4.
Incremented or decremented value of PWM duty cycle
is set in this register.
16-bit register used only in complementary PWM mode.
Sets the offset value (the dead time) between TCNT_4
and TCNT_3.
Register used only in complementary PWM mode.
Sets the upper limit (1/2 the carrier cycle) of TCNT_4.
Register used only in complementary PWM mode.
Buffer register for the TCDR.
Sets the same as the value in TCDR.
Sets output operation in complementary PWM mode.
• PSYE = B'1: Toggled output in synchronization with
the PWM cycle is enabled.
• TOCL = B'0:
Writing to the TOCS, OLSN, and OLSP bits is
enabled.
• TOCS = B'0: Selects use of the TOCR1 setting
• OLSN = B'0: Selects levels for inverse output in
complementary PWM mode.
Initial output = high, active level = low
• OLSP = B'0: Selects levels for output of positive
signals in complementary PWM mode.
Initial output = high, active level = low
Sets operation mode (channel 3).
• BFB = B'1:
TGRB and TGRD are used together (buffered
operation)
• BFA = B'1:
TGRA and TGRC are used together (buffered
operation)
• MD[3:0] = B'1111:
Complementary PWM mode 3 (transfer at crest and
trough)
REJ06B0887-0100/Rev.1.00
June 2009
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