SH7137_09 Datasheet, PDF (17/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
2.5 Settings of Registers in the Sample Program
The following describes the settings of registers used in the sample program.
2.5.1 Clock Pulse Generator (CPG)
Table 7 gives a list of settings for registers of the clock pulse generator (CPG).
Table 7 Clock Pulse Generator (CPG)
Register Name
Frequency control
register (FRQCR)
Address
H'FFFFE800
Setting
H'0241
Description
Specifies division ratios for operating frequency
• IFC[2:0] = B'000: ×1, internal clock (Iφ)
• BFC[2:0] = B'001: ×1/2, bus clock (Bφ)
• PFC[2:0] = B'001: ×1/2, peripheral clock (Pφ)
• MIFC[2:0] = B'000: ×1, MTU2S clock (MIφ)
• MPFC[2:0] = B'001: ×1/2, MTU2 clock (MPφ)
2.5.2 Power-Down Modes
Table 8 gives register settings related to low-power modes.
Table 8 Power-Down Modes
Register Name
Standby control
register 4 (STBCR4)
Address
H'FFFFE808
Setting
H'BF
Description
Settings for the operation of various modules
• MSTP23 = B'1: Clock supply to MTU2S halted.
• MSTP22 = B'0: MTU2 runs.
• MSTP21 = B'1: Clock supply to CMT halted.
• MSTP20 = B'1: Clock supply to A/D_1 halted.
• MSTP19 = B'1: Clock supply to AD_0 halted.
REJ06B0887-0100/Rev.1.00
June 2009
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