SH7137_09 Datasheet, PDF (6/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
The followings are register functions of channel 3 and 4 when complementary PWM mode is set.
• Timer general register A_3 (TGRA_3)
TGRA_3 functions as a compare match register. The upper limit (1/2 carrier cycle + dead time) for counting is set
here. Moreover, when the value in this register is changed during timer operation, the new value is that set in timer
general register C_3 (TGRC_3).
• Timer general register B_3 (TGRB_3)
TGRB_3 functions as a comparison register. The duty cycle of the PWM waveforms which are output from pins
TIOC3B and TIOC3D is set by the values in this register. Moreover, when the value in this register is changed
during timer operation, the new value is that set in timer general register D_3 (TGRD_3).
• Timer general register C_3 (TGRC_3)
TGRC_3 functions as the buffer register for TGRA_3. During timer operation, the values set in this register are
written to TGRA_3.
• Timer general register D_3 (TGRD_3)
TGRD_3 functions as the buffer register for TGRB_3. During timer operation, the values set in this register are
written to TGRB_3.
• Timer general register A_4 (TGRA_4)
TGRA_4 functions as a comparison register. The duty cycle of PWM the waveforms which are output from pins
TIOC4A and TIOC4C are set in this register. Moreover, when the value in this register is changed during timer
operation, the value is that set in the timer general register C_4 (TGRC_4).
• Timer general register B_4 (TGRB_4)
TGRB_4 functions as a comparison register. The duty cycle of the PWM waveforms which are output from pins
TIOC4B and TIOC4D are set in this register. Moreover, when the value in this register is changed during timer
operation, the value to be changed is set in the timer general register D_4 (TGRD_4).
• Timer general register C_4 (TGRC_4)
TGRC_4 functions as a buffer register for TGRA_4. During timer operation, the values set in this register are
written to TGRA_4.
• Timer general register D_4 (TGRD_4)
TGRD_4 functions as a buffer register for TGRB_4. During timer operation, the values set in this register are
written to TGRB_4.
• Temporary registers 1, 2, and 3 (Temp1, 2, and 3)
Temporary registers 1, 2, and 3 are between the respective buffer and comparison registers. Data written in a buffer
register are transferred to the corresponding temporary register and then to the comparison register. The temporary
registers cannot be accessed by the CPU.
• Timer counter _3 (TCNT_3)
TCNT_3 is a 16-bit counter. TCNT_3 decrementation on compare matches with TGRA_3, and incrementation on
compare matches with the timer dead-time data register (TDDR).
• Timer counter _4 (TCNT_4)
TCNT_4 is a 16-bit counter. TCNT_4 decrementation on compare matches with the timer cycle data register
(TCDR), and incrementation when timer counting reaches H'0000.
• Timer dead time data register (TDDR)
The TDDR is a 16-bit readable and writable register. The dead time for the PWM waveforms is set in this register.
• Timer cycle data register (TCDR)
The TCDR is a 16-bit register. The setting in this register defines half of the cycle for the PWM carrier.
• Timer cycle buffer register (TCBR)
The TCBR functions as the buffer register for the TCDR. During timer operation, the values set in this register are
written to TCDR.
REJ06B0887-0100/Rev.1.00
June 2009
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