SH7137_09 Datasheet, PDF (16/24 Pages) Renesas Technology Corp – Output of Complementary Pairs of PWM Signals in Three Phases

SH7280 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases
(Complementary PWM Mode)
2.4.4 Initialization of Pin Function Controller (PFC)
Figure 14 shows the flow for initialization of the PFC.
pfc_init()
Set port E control register L4
(PECRL4)
Set port E control register L3
(PECRL3)
Set port E I/O register L
(PEIORL)
END
[1] Setting functions of multiplexed pins on port E
• PE15MD[2:0] bits = B'110: Specifies the TIOC4D function (MTU2) for PE15.
• PE14MD[2:0] bits = B'110: Specifies the TIOC4C function (MTU2) for PE14.
• PE13MD[2:0] bits = B'110: Specifies the TIOC4B function (MTU2) for PE13.
[1]
• PE12MD[2:0] bits = B'110: Specifies the TIOC4A function (MTU2) for PE12.
[2] Setting functions of multiplexed pins on port E
• PE11MD[2:0] bits = B'110: Specifies the TIOC3D function (MTU2) for PE11.
[2]
• PE9MD[2:0] bits = B'110: Specifies the TIOC3B function (MTU2) for PE9.
• PE8MD[2:0] bits = B'110: Specifies the TIOC3A function (MTU2) for PE8.
[3] Setting input and output directions for port E pins (PE15 to PE0)
[3]
• PE15IOR bit = B'1: Specifies the TIOC4D pin (PE15) for output.
• PE14IOR bit = B'1: Specifies the TIOC4C pin (PE14) for output.
• PE13IOR bit = B'1: Specifies the TIOC4B pin (PE13) for output.
• PE12IOR bit = B'1: Specifies the TIOC4A pin (PE12) for output.
• PE11IOR bit = B'1: Specifies the TIOC3D pin (PE11) for output.
• PE9IOR bit = B'1: Specifies the TIOC3B pin (PE9) for output.
• PE8IOR bit = B'1: Specifies the TIOC3A pin (PE8) for output.
Figure 14 Initialization of Pin Function Controller (PFC)
2.4.5 Handling of the Compare Match Interrupt
Figure 15 shows the flow for handling the compare match interrupt (TGRA_3) from MTU2.
int_mtu2_tgia3()
Clear interrupt flag of TGRA_3
[1]
[1] Clearing an interrupt source flag
• TGFA bit = B'0: Compare flag A of timer status register_3
(TSR_3) is cleared.
To clear the flag, write 0 to this bit after having read it as 1.
[2]
Pul_pwm_duty1 == 0?
Yes
No
[3]
Is Pul_pwm_duty1
greater than the PWM cycle?
No
[2] [3] Setting flags
Flag (the variable Duty_select) to judge the need
to increment or decrement of the PWM duty cycle
0→Duty_select
Setting for incrementation
Yes
1→Duty_select
Setting for decrementation
is set.
• If the duty cycle is 0, the setting for
incrementation is made (0→Duty_select).
• If the duty cycle is greater than the PWM cycle, the
setting for decrementation is made (1→Duty_select).
[4]
No
Duty_select == 0?
Yes
Incrementation of settings for duty cycle
Pul_pwm_duty1 ++
Pul_pwm_duty2 ++
Pul_pwm_duty3 ++
Decrementation of settings for duty cycle
Pul_pwm_duty1 −−
Pul_pwm_duty2 −−
Pul_pwm_duty3 −−
[4] Flag judgment
Settings for PWM duty cycle are incremented or
decremented.
Pul_pwm_duty1→TGRD_3
Pul_pwm_duty2→TGRC_4
Pul_pwm_duty3→TGRD_4
END
[5]
[5] Setting PWM duty cycle in registers
• Buffer register TGRD_3: Duty cycle for PWM1 output (positive/inverse) is set.
• Buffer register TGRC_4: Duty cycle for PWM2 output (positive/inverse) is set.
• Buffer register TGRD_4: Duty cycle for PWM3 output (positive/inverse) is set.
Figure 15 Interrupt Handling
REJ06B0887-0100/Rev.1.00
June 2009
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