R1EV58256BXXN Datasheet, PDF (8/25 Pages) Renesas Technology Corp – 256K EEPROM (32-Kword × 8-bit)

R1EV58256BxxN Series/R1EV58256BxxR Series
Write Cycle
Parameter
Symbol Min*³ Typ Max Unit Test conditions
Address setup time
t_AS
0


ns
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
t_AH
50


ns
t_CS
0


ns
t_CH
0


ns
t_WS
0


ns
t_WH
0


ns
t_OES
0


ns
t_OEH
0


ns
Data setup time
t_DS
70


ns
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
t_DH
0

t_WP
0.200 
t_CW
0.200 
—
ns
30
s
30
s
Data latch time
t_DL
100


ns
Byte load cycle
t_BLC
0.3

30
µs
Byte load window
Write cycle time
t_BL
100


µs
t_WC


10*⁴ ms
Time to device busy
Write start time
Reset protect time*²
Reset high time*^{2, 6}
t_DB
120


ns
t_DW
0*⁵


ns
t_RP
100


µs
t_RES
1


µs
Notes: 1. t_DF and t_DFR are defined as the time at which the outputs achieve the open circuit conditions and are no
longer driven.
2. This function is supported by only the R1EV58256BxxR series.
3. Use this device in longer cycle than this value.
4. t_WC must be longer than this value unless polling techniques or RDY/Busy (only the R1EV58256BxxR series)
are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t_DW if polling techniques or RDY/Busy (only the
R1EV58256BxxR series) are used.
6. This parameter is sampled and not 100 tested.
7. A6 through A14 are page addresses and these addresses are latched at the first falling edge of WE.
8. A6 through A14 are page addresses and these addresses are latched at the first falling edge of CE.
9. See AC read characteristics.
R10DS0208EJ0200 Rev.2.00
May 12, 2016
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