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R1EV58256BXXN Datasheet, PDF (5/25 Pages) Renesas Technology Corp – 256K EEPROM (32-Kword × 8-bit)
R1EV58256BxxN Series/R1EV58256BxxR Series
DC Characteristics
Parameter
Input leakage current
Output leakage current
Standby VCC current
Operating VCC current
Symbol
Min
Typ
Max
ILI


2*1
ILO


2
ICC1


20
ICC2


1
ICC3


8


12


12


30
Output low voltage
VOL


0.4
Output high voltage
VOH
VCC  0.8


Note: 1. ILI on RES = 100 A max (only the R1EV58256BXXR series)
Capacitance
Parameter
Input capacitance*1
Output capacitance*1
Symbol
Min
Typ
Cin


Cout


Note: 1. This parameter is periodically sampled and not 100 tested.
(Ta = –40 to +85C, VCC = 2.7 to 5.5 V)
Unit
Test conditions
A VCC = 5.5 V, Vin = 5.5 V
A VCC = 5.5 V, Vout = 5.5/0.4 V
A CE = VCC
mA CE = VIH
mA Iout = 0 mA, Duty = 100,
Cycle = 1 s, VCC = 3.6 V
mA Iout = 0 mA, Duty = 100,
Cycle = 1 ns, VCC = 5.5 V
mA Iout = 0 mA, Duty = 100,
Cycle = 120 s, VCC = 3.6 V
mA Iout = 0 mA, Duty = 100,
Cycle = 120 ns, VCC = 5.5 V
V IOL = 2.1 mA
V IOH = 400 A
(Ta = +25°C, f = 1 MHz)
Max Unit
Test conditions
6
pF Vin = 0 V
12
pF Vout = 0 V
AC Characteristics
Test Conditions
 Input pulse levels: 0.4 V to 3.0 V, 0 V to VCC (RES pin*2)
 Input rise and fall time:  5 ns
 Input timing reference levels: 0.8, 2.0 V
 Output load: 1TTL Gate +100 pF
 Output reference levels: 1.5 V, 1.5 V
Read Cycle
Parameter
Address to output delay
CE to output delay
OE to output delay
Address to output hold
OE (CE) high to output float*1
RES low to output float*1, 2
RES to output delay*2
Symbol
tACC
tCE
tOE
tOH
tDF
tDFR
tRR
Min


10
0
0
0
0
Max
85
85
40

40
350
450
(Ta = –40 to +85C, VCC = 4.5V to 5.5V)
Unit
ns
ns
ns
ns
ns
ns
ns
Test conditions
CE = OE = VIL,WE = VIH
OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL,WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL,WE = VIH
CE = OE = VIL,WE = VIH
R10DS0208EJ0200 Rev.2.00
May 12, 2016
Page 5 of 23