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R1EV58256BXXN Datasheet, PDF (6/25 Pages) Renesas Technology Corp – 256K EEPROM (32-Kword × 8-bit) | |||
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R1EV58256BxxN Series/R1EV58256BxxR Series
Write Cycle
Parameter
Symbol Min*3 Typ Max Unit Test conditions
Address setup time
tAS
0
ï¾
ï¾
ns
Address hold time
CE to write setup time (WE controlled)
CE hold time (WE controlled)
WE to write setup time (CE controlled)
WE hold time (CE controlled)
OE to write setup time
OE hold time
tAH
50
ï¾
ï¾
ns
tCS
0
ï¾
ï¾
ns
tCH
0
ï¾
ï¾
ns
tWS
0
ï¾
ï¾
ns
tWH
0
ï¾
ï¾
ns
tOES
0
ï¾
ï¾
ns
tOEH
0
ï¾
ï¾
ns
Data setup time
tDS
50
ï¾
ï¾
ns
Data hold time
WE pulse width (WE controlled)
CE pulse width (CE controlled)
tDH
0
ï¾
tWP
0.100 ï¾
tCW
0.100 ï¾
ï¾
ns
30
ïs
30
ïs
Data latch time
tDL
50
ï¾
ï¾
ns
Byte load cycle
tBLC
0.2
ï¾
30
ïs
Byte load window
Write cycle time
tBL
100
ï¾
â
ïs
tWC
ï¾
ï¾
10*4 ms
Time to device busy
Write start time
Reset protect time*2
Reset high time*2, 6
tDB
120
ï¾
ï¾
ns
tDW
0*5
ï¾
ï¾
ns
tRP
100
ï¾
ï¾
ïs
tRES
1
ï¾
ï¾
ïs
Notes: 1. tDF and tDFR are defined as the time at which the outputs achieve the open circuit conditions and are no longer
driven.
2. This function is supported by only the R1EV58256BxxR series.
3. Use this device in longer cycle than this value.
4. tWC must be longer than this value unless polling techniques or RDY/Busy (only the R1EV58256BxxR series)
are used. This device automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after tDW if polling techniques or RDY/Busy (only the
R1EV58256BxxR series) are used.
6. This parameter is sampled and not 100ï¥ tested.
7. A6 through A14 are page address and these addresses are latched at the first falling edge of WE.
8. A6 through A14 are page address and these addresses are latched at the first falling edge of CE.
9. See AC read characteristics.
R10DS0208EJ0200 Rev.2.00
May 12, 2016
Page 6 of 23
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