R1EV58256BXXN Datasheet, PDF (17/25 Pages) Renesas Technology Corp – 256K EEPROM (32-Kword × 8-bit)

R1EV58256BxxN Series/R1EV58256BxxR Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write cycle. Following
the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each additional byte load cycle
must be started within 30 µs from the preceding falling edge of WE or CE. When CE or WE is high for 100 µs after
data input, the EEPROM enters write mode automatically and the input data are written into the EEPROM.
Data Polling
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read mode during a
write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the EEPROM is performing a write
operation.
RDY/Busy Signal (only the R1EV58256BxxR series)
RDY/Busy signal also allows the status of the EEPROM to be determined. The RDY/Busy signal has high impedance
except in write cycle and is lowered to V_OL after the first write signal. At the end of a write cycle, the RDY/Busy signal
changes state to high impedance.
RES Signal (only the R1EV58256BxxR series)
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by keeping RES low
when V_CC is switched. RES should be high during read and programming because it doesn't provide a latch function.
V_CC
RES
Read inhibit
Read inhibit
Program inhibit
Program inhibit
WE, CE Pin Operation
During a write cycle, addresses are latched by the falling edge of WE or CE, and data is latched by the rising edge of
WE or CE.
Write/Erase Endurance and Data Retention Time
The endurance is 10⁵ cycles (1% cumulative failure rate). The data retention time is more than 10 years.
R10DS0208EJ0200 Rev.2.00
May 12, 2016
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