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| R1EV58256BXXN Datasheet, PDF (19/25 Pages) Renesas Technology Corp – 256K EEPROM (32-Kword × 8-bit) | |||
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R1EV58256BxxN Series/R1EV58256BxxR Series
2. Data Protection at VCC On/Off
When VCC is turned on or off, noise on the control pins generated by external circuits (CPU, etc) may act as a trigger
and turn the EEPROM to program mode by mistake. To prevent this unintentional programming, the EEPROM
must be kept in an unprogrammable state while the CPU is in an unstable state.
Note: The EPROM should be kept in unprogrammable state during VCC on/off by using CPU RESET signal.
VCC
CPU
RESET
* Unprogrammable
* Unprogrammable
2.1 Protection by CE, OE, WE
To realize the unprogrammable state, the input level of control pins must be held as shown in the table below.
CE
VCC
ï´
ï´
OE
ï´
VSS
ï´
WE
ï´
ï´
VCC
ï´: Donât care.
VCC: Pull-up to VCC level.
VSS: Pull-down to VSS level.
2.2 Protection by RES (only the R1EV58256BxxR series)
The unprogrammable state can be realized by that the CPUâs reset signal inputs directly to the EEPROMâs RES
pin. RES should be kept VSS level during VCC on/off.
The EEPROM breaks off programming operation when RES becomes low, programming operation doesnât
finish correctly in case that RES falls low during programming operation. RES should be kept high for 10 ms
after the last data input.
VCC
RES
WE
or CE
Program inhibit
1 µs min 100 µs min
Program inhibit
10 ms min
R10DS0208EJ0200 Rev.2.00
May 12, 2016
Page 19 of 23
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